The present invention relates to electrical techniques for controlling the threshold voltage of access transistors in DRAM cells. More particularly, the invention relates to low voltage generators for applying a low voltage to a memory array bitline.
Many types of integrated circuit designs now commonly contain memory arrays embedded within logic-based chips. Such designs improve performance by providing on-chip memory, thereby reducing the number of input-output (I/O) operations between the processor and a general purpose RAM. Embedded memory is becoming particularly important in custom integrated circuits such as application specific integrated circuits (ASICs) and programmable logic devices (PLDs). It is also used for many specialized applications such as printer and graphics integrated circuits.
Embedded memory often takes the form of DRAM arrays. Each DRAM cell includes an access transistor and a storage capacitor. To prevent unacceptable levels of charge leakage through the access transistor, that transistor's threshold voltage is purposely set high. If the threshold voltage is set too low, the access transistor will leak too much current and possibly lose data. To address this issue, most dedicated DRAM chips employ a process technology such as a high Vt channel implant which raises the threshold voltage to a level that holds back significant leakage.
For performance reasons, most logic-based integrated circuits are designed with transistors that operate at lower threshold voltages than DRAM access transistors. If an embedded memory integrated circuit is fabricated with a process suitable for logic circuits (low threshold voltage), DRAM leakage may be unacceptable. If the integrated circuit is fabricated with a process suitable for DRAMs (high threshold voltage), performance may suffer. A fabrication process could be designed such that MOS transistors in the logic and memory sections of the integrated circuit are processed differently (to impart different threshold voltages). However, this introduces additional process steps which increases the manufacturing cost.
For these reasons, improved techniques for controlling the threshold voltage DRAM cells in embedded memory applications would be desirable.